IEEE Blended Learning Program

IEEE BLENDED LEARNING PROGRAM FOR VLSI
MEMBERS LIST
S.No
Name of the Student
Academic Year
Course Name
Status
1
R.KALIDASAN2015 - 2016 Logic DesignCompleted
2
R.HARIPRASAATH2015 - 2016 Logic DesignCompleted
3
M.HARIHARASUDHAN2015 - 2016 Logic DesignCompleted
4
G.ARUNKUMAR2015 - 2016 Logic DesignCompleted
5
R.MANGAIYARKARASI2015 - 2016 Logic DesignCompleted
6
N.DEEPAMBIKA2015 - 2016 Logic DesignCompleted
7
T.DEEPASRI2015 - 2016 Logic DesignCompleted
8
P.DHARINI2015 - 2016 Logic DesignCompleted
9
M.GOKUL PRIYA2015 - 2016 Logic DesignCompleted
10
V.SRIDHAR2015 - 2016 Logic DesignCompleted
11
M.THAMARAI KANNAN2015 - 2016 Logic DesignCompleted
12
S.SARAVANAN2015 - 2016 Logic DesignCompleted
13
S.KANIMOZHI2015 - 2016 Logic DesignCompleted
14
G.KEERTHI2015 - 2016 Logic DesignCompleted
15
M.DIVYA2015 - 2016 Logic DesignCompleted
16
B.GOWSITHA2015 - 2016 Logic DesignCompleted
17
K.BHUVANESHWARI2015 - 2016 Logic DesignCompleted
18
B.ABIRAMI2015 - 2016 Logic DesignCompleted
19
M.NAGADHARANI2015 - 2016 Logic DesignCompleted
20
S.S.SOWNDHARYA LAKSHMI2015 - 2016 Logic DesignCompleted
21
M.PUNITHA2015 - 2016 Logic DesignCompleted
22
P.VIJAYA LAKSHMI2015 - 2016 Logic DesignCompleted
23
S.HEMA2015 - 2016 Logic DesignCompleted
24
E.PRIYA2015 - 2016 Logic DesignCompleted
25
K.K.RANJITH2015 - 2016 Logic DesignCompleted
26
K.VENUSANKARAN2015 - 2016 Logic DesignCompleted
27
G.GOKUL2015 - 2016 Logic DesignCompleted
28
M.ABINAYA2015 - 2016 Logic DesignCompleted
29
P.SURESHBABU2015 - 2016 Static Timing Analysis for VLSI EngineersCompleted
30
P.MOHAN2015 - 2016 Static Timing Analysis for VLSI EngineersCompleted
Event Photos
DSC03635DSC03801
Share this Info                                      Tweet about this on TwitterShare on FacebookGoogle+Digg thisShare on RedditShare on LinkedInEmail to someone
Menu