IEEE Blended Learning Program

IEEE BLENDED LEARNING PROGRAM FOR VLSI MEMBERS LIST
S.No	Name of the Student	Academic Year	Course Name	Status
1	R.KALIDASAN	2015 - 2016	Logic Design	Completed
2	R.HARIPRASAATH	2015 - 2016	Logic Design	Completed
3	M.HARIHARASUDHAN	2015 - 2016	Logic Design	Completed
4	G.ARUNKUMAR	2015 - 2016	Logic Design	Completed
5	R.MANGAIYARKARASI	2015 - 2016	Logic Design	Completed
6	N.DEEPAMBIKA	2015 - 2016	Logic Design	Completed
7	T.DEEPASRI	2015 - 2016	Logic Design	Completed
8	P.DHARINI	2015 - 2016	Logic Design	Completed
9	M.GOKUL PRIYA	2015 - 2016	Logic Design	Completed
10	V.SRIDHAR	2015 - 2016	Logic Design	Completed
11	M.THAMARAI KANNAN	2015 - 2016	Logic Design	Completed
12	S.SARAVANAN	2015 - 2016	Logic Design	Completed
13	S.KANIMOZHI	2015 - 2016	Logic Design	Completed
14	G.KEERTHI	2015 - 2016	Logic Design	Completed
15	M.DIVYA	2015 - 2016	Logic Design	Completed
16	B.GOWSITHA	2015 - 2016	Logic Design	Completed
17	K.BHUVANESHWARI	2015 - 2016	Logic Design	Completed
18	B.ABIRAMI	2015 - 2016	Logic Design	Completed
19	M.NAGADHARANI	2015 - 2016	Logic Design	Completed
20	S.S.SOWNDHARYA LAKSHMI	2015 - 2016	Logic Design	Completed
21	M.PUNITHA	2015 - 2016	Logic Design	Completed
22	P.VIJAYA LAKSHMI	2015 - 2016	Logic Design	Completed
23	S.HEMA	2015 - 2016	Logic Design	Completed
24	E.PRIYA	2015 - 2016	Logic Design	Completed
25	K.K.RANJITH	2015 - 2016	Logic Design	Completed
26	K.VENUSANKARAN	2015 - 2016	Logic Design	Completed
27	G.GOKUL	2015 - 2016	Logic Design	Completed
28	M.ABINAYA	2015 - 2016	Logic Design	Completed
29	P.SURESHBABU	2015 - 2016	Static Timing Analysis for VLSI Engineers	Completed
30	P.MOHAN	2015 - 2016	Static Timing Analysis for VLSI Engineers	Completed
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